Nano-devices will emerge only if the technological variability inherent to their scale can be handled. With their intrinsic tolerance to defects and auto-compensation capabilities, neuromorphic architectures allow lifting this roadblock. Nano-memristors, which are non-volatile programmable resistors, are ideally suited to be used as synapses in such architectures. We aim at studying a new class of scaled-down organic memory devices, building arrays of such devices, interfacing these memory blocks with CMOS electronics, proposing the associated learning algorithms and implementing such architectures.
The presentation of the communications of the CHIST-ERA Conference 2012 (keynote and short talks, posters) will be continuously updated in the course of June.
Dr. Vincent Derycke is researcher at the French national research organism CEA and head of Molecular Electronics Laboratory (LEM) group of the Laboratory of Condensed Matter Physics within the Saclay Institute of Matter and Radiation (IRAMIS).
|Poster Vincent Derycke.pdf||1.89 MB|
Dr. Weisheng Zhao is research associate in the Spintronics group of the Fundamental Electronics Institute (IEF), Orsay, France.
In this proposal, we plan to design a new computing architecture based processor by integrating non-volatile memory elements among the operators of treatment and making the processor non-volatile itself. This approach can completely overcome the power and speed bottlenecks of the Von-Neumann architecture due to the separation between memory and central processing unit. An ideal architecture, called "Logic in memory", will be in particular evaluated benefiting from the experimental demonstrations of emerging nonvolatile nanodevices like racetrack memory and Spin-RAM.
|Poster Weisheng Zhao.pdf||616.69 KB|
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